Typical solid state memory devices (dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM) employ micro-electronic circuit elements for each memory bit in memory applications. Since one or more electronic circuit elements are required for each memory bit, these devices consume considerable chip space to store information, limiting chip density. For typical non-volatile memory elements (like EEPROM i.e. “flash” memory), floating gate field effect transistors are employed as the data storage device. These devices hold a charge on the gate of the field effect transistor to store each memory bit and have limited re-programmability. They are also slow to program.
Phase Change Access Memory devices (also known as PRAM or Ovonic memory devices) use phase change materials (PCMs) that can be electrically switched between an insulating amorphous and conductive crystalline state for electronic memory application. Typical materials suited for these applications utilize various chalcogenide (Group VIB) and Group VB elements of the periodic table (e.g., Te, Po, and Sb) in combination with one or more of In, Ge, Ga, Sn, or Ag (sometimes referred to as a “phase change alloy”). Particularly useful phase change alloys are germanium (Ge)-antimony (Sb)-tellurium (Te) alloys (GST alloys), such as an alloy having the formula Ge2Sb2Te5 (GST225). These materials can reversibly change physical states depending on heating/cooling rates, temperatures, and times.
Compositions and methods for chemical-mechanical polishing (CMP) the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries, CMP slurries, and CMP compositions) for CMP of metal-containing surfaces of semiconductor substrates (e.g., integrated circuits) typically contain an oxidizing agent, various additive compounds, abrasives, and the like.
In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate, urging the substrate against the polishing pad. The pad and carrier, with its attached substrate, are moved relative to one another. The relative movement of the pad and substrate serves to abrade the surface of the substrate to remove a portion of the material from the substrate surface, thereby polishing the substrate. The polishing of the substrate surface typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition.
GST alloys having an increased amount of antimony and a decreased amount of tellurium relative to GST225 are increasingly being used as a phase-change alloy in electronic circuits. These antimony-rich GST alloys are “softer” relative to conventional GST alloys, because the lower tellurium content makes the GST alloy easier to oxidize and remove. Polishing these antimony-rich GST alloys with conventional CMP techniques results in an unacceptably high level of defects and distortions on the surface of the polished GST alloys. There is a significant need for CMP compositions and techniques having a GST removal rate lower than conventional CMP compositions that can be used to polish the “softer” antimony-rich GST alloys and limit surface defects.
Conventional CMP compositions and techniques for removal of GST alloys are generally designed to remove GST layers while avoiding or minimizing the removal of dielectric material such as silicon nitride (Si3N4). The ratio of the removal rates of a GST layer to the removal rate of a dielectric base layer is called the “selectivity” or “removal rate ratio” for removal of GST in relation to dielectric during CMP processing. Previously, it was believed that the removal rate of the GST layer must greatly exceed the removal rate of the dielectric layer (e.g. high GST selectivity) so that polishing effectively stops when elevated portions of the dielectric are exposed. In some emerging electrical circuit designs, however, there is a need for a CMP application to remove both GST alloys and silicon nitride. Known polishing compositions and methods do not provide the ability to remove GST alloys and silicon nitride at desired removal rates and removal rate ratios.
The compositions and methods of the present invention address the challenges associated with polishing softer GST alloys and in some embodiments, the need for removal of silicon nitride along with GST.